15 Juni 2013

Mengikuti ICISS 2013

بسم الله الرحمن الرحيم


Pada kesempatan kemarin, saya mengikuti sebuah ICT conference yang diadakan oleh STEI ITB di Jakarta, yaitu International Conference on ICT for Smart Society (http://stei.itb.ac.id/iciss2013/). Pada kesempatan tersebut, saya mempresentasikan paper saya yang berjudul "A Novel Fixed-Point Square Root Algorithm and Its Digital Hardware Design" dan "VLSI Design of Parallel Sorter based on Modified PCM Algorithm and Batcher's Odd-Even Mergesort". Alhamdulillah, acara berjalan dengan lancar. Sama seperti harapan saya sebelumnya, semoga acara diskusi, konferensi, dan presentasi karya ilmiah semacam ini tidak hanya untuk kejayaan karir pribadi seseorang, namun semoga menjadi suatu tamasya ilmiah, menyegarkan pikiran dan ide dengan hal-hal baru dan ide-ide baru yang muncul dari riset orang lain. Sehingga bisa bermanfaat baik langsung maupun tidak langsung terhadap pribadi dan masyarakat, dan yang paling penting semoga berkah Allah ada di sana. Aamiin..

Berikut judul dan abstrak paper yang saya submit:

[Paper 1]
A Novel Fixed-Point Square Root Algorithm and Its Digital Hardware Design

Abstract— Square root operation is one of the basic important operation in digital signal processing. It will calculate the square root value from the given input. This operation is known hard to implement in digital hardware because of the complexity of its algorithm. There were many researches related to this topic to obtain the optimum design between area consumption and speed. Regarding this condition, we propose an alternative square root algorithm which is based on two approaches, digital binary input decomposition and iterative calculation. Its fixed-point digital hardware implementation is very simple, low complexity, and resource-efficient. It doesn’t need any correction adjustments and directly produces accurate value of square root result and remainder in (N/2)+1 clock cycles, which N represents the wordlength of input. This design has been synthesized for FPGA target board Altera Cyclone II EP2C35F672C6 and produced good results in resource consumption and speed.  

Keywords— Novel square root algorithm; iterative calculation; fixed-point; simple; low complexity; resource-efficient

[Paper 2]
VLSI Design of Parallel Sorter based on Modified PCM Algorithm and Batcher’s Odd-Even Mergesort 

Abstract— Data sorting is an important process in digital signal processing. There were many researches related to data sorting, two of them were about partition and concurrent merging (PCM)  algorithm and Batcher’s odd-even mergesort network. PCM algorithm will decompose the data in several groups and sort them in two phases, quicksort and mergesort. We captured and modified the idea of PCM algorithm by eliminating unnecessary processes which can be handled directly by Batcher’s odd-even mergesort architecture. VLSI design of this parallel sorter is low complexity. It has 2k+1 clock cycles latency, which k represents the number of iterative steps for each kind of sorter block (odd or even). This design has been synthesized for FPGA Altera Cyclone II EP2C35F672C6 as target board.

Keywords— Parallel sorter; VLSI design; low complexity; modified PCM algorithm, Batcher’s odd-even mergesort 

1 respon:

Devid Haryalesmana Wahid mengatakan...

Huhu... kapan saya punya paper... :P

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